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visit our website: www.e2v.com for the latest version of the datasheet e2v semiconductors sas 2009 pc7448 powerpc 7448 risc microprocessor datasheet features ? 3000 dhrystone 2.1 mips at 1.3 ghz ? selectable bus clock (30 cpu bus dividers up to 28x) ? selectable mpx/60x interface voltage (1.5v; 1.8v; 2.5v) ? p d typically 10w at 1.25 ghz at v dd = 1.1v full operating conditions ? nap, doze and sleep power saving modes ? superscalar (four instructions fetched per clock cycle) ? 4 gb direct addressing range ? virtual memory: 4 hexabytes (2 52 ) ? 64-bit data and 36-bit address bus interface ? integrated l1: 32 kb instruction and 32 kb data cache ? integrated l2: 1 mb with ecc ? 11 independent execution un its and 3 register files ? write-back and write-through operations ? f int max = 1267 mhz ? f bus max = 133 mhz/166 mhz and 200 mhz description this document is primarily concerned with the power architecture ? pc7448. the pc7448 is an implementation of the powerpc microprocessor family of reduced instruction set computer (risc) microprocessors. this document describes pertinent electrical and physical charac teristics of the pc7448. for information regarding specific pc7448 part numbers covered by this document and part numbers covered by other documents, see ?ordering information? on page 52. ? for functional characteristics of the processor, refer to the pc7450 risc microprocessor family reference manual . screening ? full military temperature range (t c = ?55 c, t j = +125 c) ? industrial temperature range (t c = ?40 c, t j = +110 c) 0814g?hirel?04/09
2 0814g?hirel?04/09 pc7448 e2v semiconductors sas 2009 1. overview the pc7448 is the sixth implementation of fourth-generation (g4) microprocessors from freescale ? . the pc7448 implements the full powerpc 32 bits architecture and is targeted at networking and com- puting systems applications. the pc7448 consists of a processor core and a 1 mbyte l2. figure 1-1 on page 3 shows a block diagram of the pc7448. the core is a high-performance superscalar design supporting a double-precision floating-point unit and a simd multimedia unit. the memory storage subsystem supports the mpx bus protocol and a subset of the 60x bus protocol to main memory and other system resources.
3 0814g?hirel?04/09 e2v semiconductors sas 2009 pc7448 figure 1-1. pc7448 block diagram + integer reservation station unit 2 + integer reservation station unit 2 additional features ? time base counter/decrementer clock multiplier jtag/cop interface thermal/power management performance monitor out-of-order issue of altivec instr. + + x fpscr fpscr pa + x instruction unit instruction queue (12-word) 96-bit (3 instructions) reservation integer 128-bit (4 instructions) 32-bit floating- point unit 64-bit reservation load/store unit (ea calculation) finished 32-bit (16-entry) tags 32-kbyte d cache 36-bit 64-bit integer stations (2) reservation station reservation stations (2) fpr file 16 rename buffers stations (2-entry) gpr file 16 rename buffers reservation station vr file 16 rename buffers 64-bit 128-bit 128-bit completed instruction mmu srs (shadow) 128-entry ibat array itlb tags 32-kbyte i cache stores stores load miss vector to u c h queue (3) vr issue fpr issue branch processing unit ctr lr btic (128-entry) bht (2048-entry) fetcher gpr issue (6-entry/3-issue) (4-entry/2-issue) (2-entry/1-issue) dispatch unit data mmu srs (original) 128-entry dbat array dtlb vector touch engine 32-bit ea l1 castout status l2 store queue (l2sq) vector fpu reservation station reservation station reservation station vector integer unit 1 vector integer unit 2 vector permute unit line tags block 0 (32-byte) status block 1 (32-byte) memory subsystem snoop push/ interventions l1 castouts bus accumulator l1 push (4) unit 2 unit 1 l1 load queue (llq) l1 load miss (5) cacheable store miss (2) instruction fetch (2) l1 service l1 store queue (lsq) system bus interface l2 prefetch (3) address bus data bus queues castout bus store queue push load queue (11) queue (5) / queue (6) 1 1-mbyte unified l2 cache controller completion queue completion unit completes up to th ree per clock instructions notes: the castout queue and push queue share resources such for a combined total of 6 entries. the castout queue itself is limited to 5 entries, ensuring 1 entry will be available for a push.
4 0814g?hirel?04/09 pc7448 e2v semiconductors sas 2009 note that the pc7448 is a footprint-compatible, drop-in replacement in an pc7447a application if the core voltages are identical. 2. features this section summarizes features of the pc7448 implementation of the powerpc architecture. major features of the pc7448 are as follows: ? high-performance, superscalar microprocessor up to four instructions can be fetched from the instruction cache at a time up to three instructions plus a branch instruction can be dispatched to the issue queues at a time up to 12 instructions can be in the instruction queue (iq) up to 16 instructions can be at some stage of execution simultaneously single-cycle execution for most instructions one instruction per clock cycle throughput for most instructions seven-stage pipeline control ? eleven independent execution units and three register files branch processing unit (bpu) features static and dynamic branch prediction ? 128-entry (32-set, four-way set-associative) branch target instruction cache (btic), a cache of branch instructions that have been encountered in branch/loop code sequences. if a target instruction is in the btic, it is fetched into the instruction queue a cycle sooner than it can be made available from the instruction cache. typically, a fetch that hits the btic provides the first four instructions in the target stream ? 2048-entry branch history table (bht) with 2 bits per entry for four levels of prediction: not taken, strongly not taken, taken, and strongly taken ? up to three outstanding speculative branches ? branch instructions that do not update the count register (ctr) or link register (lr) are often removed from the instruction stream ? eight-entry link register stack to predict the target address of branch conditional to link register ( bclr ) instructions four integer units (ius) that share 32 gprs for integer operands ? three identical ius (iu1a, iu1b, and iu1c) can execute all integer instructions except multiply, divide, and move to/from special-purpose register instructions ? iu2 executes miscellaneous instructions, including the cr logical operations, integer multiplication and division instructions, and move to/from special-purpose register instructions five-stage fpu and 32-entry fpr file ? fully ieee ? 754-1985 ? compliant fpu for both single- and double-precision operations ? supports non-ieee mode for time-critical operations ? hardware support for denormalized numbers ? thirty-two 64 bits fprs for single or double-precision operands four vector units and 32-entry vector register file (vrs).
5 0814g?hirel?04/09 e2v semiconductors sas 2009 pc7448 ? vector permute unit (vpu) ? vector integer unit 1 (viu1) handles short-latency altivec ? integer instructions, such as vector add instructions (for example, vaddsbs , vaddshs , and vaddsws ) ? vector integer unit 2 (viu2) handles longer-latency altivec integer instructions, such as vector multiply add instructions (for example, vmhaddshs , vmhraddshs , and vmladduhm ) ? vector floating-point unit (vfpu) three-stage load/store unit (lsu) ? supports integer, floating-point, and vector instruction load/store traffic ? four-entry vector touch queue (vtq) supports all four architected altivec data stream operations ? three-cycle gpr and altivec lo ad latency (byte, half word, word, vector) with one-cycle throughput ? four-cycle fpr load latency (single, double) with one-cycle throughput ? no additional delay for misaligned access within double-word boundary ? a dedicated adder calculates effective addresses (eas) ? supports store gathering ? performs alignment, normalization, and precision conversion for floating-point data ? executes cache control and tlb instructions ? performs alignment, zero padding, and sign extension for integer data ? supports hits under misses (multiple outstanding misses) ? supports both big and little-endian modes, including misaligned little-endian accesses ? three issue queues, fiq, viq, and giq, can accept as many as one, two, and three instructions, respectively, in a cycle. instruction dispatch requires the following: instructions can only be dispatched from the three lowest iq entries, iq0, iq1, and iq2 a maximum of three instructions can be dispatched to the issue queues per clock cycle space must be available in the cq for an instruction to dispatch (this includes instructions that are assigned a space in the cq but not in an issue queue) ? rename buffers 16 gpr rename buffers 16 fpr rename buffers 16 vr rename buffers ? dispatch unit decode/dispatch stage fully decodes each instruction ? completion unit retires an instruction from the 16-entry completion queue (cq) when all instructions ahead of it have been completed, the instruction has finished executing, and no exceptions are pending guarantees sequential programming model (precise exception model) monitors all dispatched instructions and retires them in order tracks unresolved branches and flushes instructions after a mispredicted branch
6 0814g?hirel?04/09 pc7448 e2v semiconductors sas 2009 retires as many as three instructions per clock cycle ? separate on-chip l1 instruction and data caches (harvard architecture) 32-kbyte, eight-way set-associative instruction and data caches pseudo least-recently-used (p lru) replacement algorithm 32-byte (eight-word) l1 cache block physically indexed/physical tags cache write-back or write-through operation programmable on a per-page or per-block basis instruction cache can provide four instructions per clock cycle; da ta cache can provide four words per clock cycle caches can be disabled in software caches can be lo cked in software mesi data cache coheren cy maintained in hardware separate copy of data cache tags for efficient snooping parity support on l1 and l2 cache and l2 tags no snooping of instruction cache except for icbi instruction data cache supports altivec lru and transient instructions critical double- and/or quad-word forwarding is performed as needed. critical quad-word forwarding is used for altivec loads and instruction fetches. other accesses use critical double-word forwarding ? level 2 (l2) cache interface on-chip, 1-mbyte, eight-way set-associative unified instruction and data cache cache write-back or write-through operation programmable on a per-page or per-block basis parity support on cache tags ecc or parity support on data error injection allo ws testing of error recovery software ? separate memory management units (mmus) for instructions and data 52-bit virtual address, 32- or 36-bit physical address address translation for 4-kbyte pages, vari able-sized blocks, an d 256-mbyte segments memory programmable as write-back/write-through, caching-inhibited/caching-allowed, and memory coherency enforced/memory coherency not enforced on a page or block basis separate ibats and dbats (eight each) also defined as sprs separate instruction and data translation lookaside buffers (tlbs) ? both tlbs are 128-entry, two-way set-associative and use an lru replacement algorithm ? tlbs are hardware- or software-reloadable (that is, a page table search is performed in hardware or by system software on a tlb miss) ? efficient data flow although the vr/lsu interface is 128 bits, the l1/l2 bus interface allows up to 256 bits
7 0814g?hirel?04/09 e2v semiconductors sas 2009 pc7448 the l1 data cache is fully pipelined to pr ovide 128 bits/cycle to or from the vrs the l2 cache is fully pipelined to provide 32 byte s per clock every other cycle to the l1 caches as many as 16 out-of-order transac tions can be present on the mpx bus store merging for multiple store misses to the same line. only coherency action taken (address- only) for store misses merged to all 32 bytes of a cache block (no data tenure needed) three-entry finished store queue and five-entry completed store queue between the lsu and the l1 data cache separate additional queues for efficient buffering of outbound data (such as castouts and write- through stores) from the l1 data cache and l2 cache ? multiprocessing support features include the following: hardware-enforced, mesi cache coherency protocols for data cache load/store with reservation instruction pair for atomic memory references, semaphores, and other multiprocessor operations ? power and thermal management dynamic frequency switching (dfs) feature allows processor core frequency to be halved or quar- tered through software to reduce power consumption the following three power-saving modes are available to the system: ? nap: instruction fetching is halted. only the clocks for the time base, decrementer, and jtag logic remain running. the part goes into the doze state to snoop memory operations on the bus and then back to nap using a qreq/qack processor-system handshake protocol ? sleep, power consumption is further reduced by disabling bus snooping, leaving only the pll in a locked and running state. all internal functional units are disabled ? deep sleep: when the part is in the sleep state, the system can disable the pll. the system can then disable the sysclk source for gr eater system power savings. power-on reset procedures for restarting and relocking the pll must be followed upon exiting the deep sleep state instruction cache throttling provides control of instruction fetching to limit device temperature a new temperature diode that can determine the temperature of the microprocessor support for core voltage derating to further reduce power consumption ? performance monitor can be used to help debug system designs and improve software efficiency ? in-system testability and de bugging features through jtag boundary-scan capability ? testability lssd scan design ieee 1149.1 jtag interface ? reliability and serviceability parity checking on system bus parity checking on the l1 caches and l2 data tags ecc or parity checking on l2 data
8 0814g?hirel?04/09 pc7448 e2v semiconductors sas 2009 3. comparison with the pc7447a and pc7447 table 3-1 compares the key features of the pc7448 with the key features of the earlier pc7447a and pc7447. all are based on the pc7450 risc microprocessor and are architecturally very similar. the pc7448 is identical to the pc7447a, but the pc7448 supports 1 mbyte of l2 cache with ecc and the use of dynamic frequency switching (dfs) with more bus-to-core ratios. table 3-1. microarchitecture comparison microarchitectural specs pc7448 pc7447a pc7447 basic pipeline functions logic inversions per cycle 18 pipeline stages up to execute 5 total pipeline stages (minimum) 7 pipeline maximum instruction throughput 3 + branch pipeline resources instruction buffer size 12 completion buffer size 16 renames (integer, float, vector) 16, 16, 16 maximum execution throughput sfx 3 vector 2 (any 2 of 4 units) scalar floating-point 1 out-of-order window size in execution queues sfx integer units 1 entry 3 queues vector units in order, 4 queues scalar floating-point unit in order branch processing resources prediction structures btic, bht, link stack btic size, associativity 128-entry, 4-way bht size 2k-entry link stack depth 8 unresolved branches supported 3 branch taken penalty (btic hit) 1 minimum misprediction penalty 6 execution unit timings (latency-throughput) aligned load (integer, float, vector) 3-1, 4-1, 3-1 misaligned load (integer, float, vector) 4-2, 5-2, 4-2 l1 miss, l2 hit latency with ecc (data/instruction) 12/16 ? l1 miss, l2 hit latency without ecc (data/instruction) 11/15 9/13 sfx (add, sub, shift, rot, cmp, logicals) 1-1
9 0814g?hirel?04/09 e2v semiconductors sas 2009 pc7448 integer multiply (32 8, 32 16, 32 32) 4-1, 4-1, 5-2 scalar float 5-1 vsfx (vector simple) 1-1 vcfx (vector complex) 4-1 vfpu (vector float) 4-1 vper (vector permute) 2-1 mmus tlbs (instruction and data) 128-entry, 2-way tablewalk mechanism hardware + software instruction bats/data bats 8/8 l1 i cache/d cache features size 32k/32k associativity 8-way locking granularity way parity on i cache word parity on d cache byte number of d cache misses (load/store) 5/2 5/1 data stream touch engines 4 streams on-chip cache features cache level l2 size/associativity 1-mbyte/ 8-way 512-kbyte/8-way access width 256 bits number of 32-byte sectors/line 2 2 parity tag byte byte parity data byte byte data ecc 64 bits ? thermal control dynamic frequency switching divide-by-two mode yes yes no dynamic frequency switching divide-by-four mode yes no no thermal diode yes yes no table 3-1. microarchitecture comparison (continued) microarchitectural specs pc7448 pc7447a pc7447
10 0814g?hirel?04/09 pc7448 e2v semiconductors sas 2009 4. general parameters the following list summarizes the general parameters of the pc7448: 5. electrical and ther mal characteristics this section provides the ac and dc electrical specifications and thermal characteristics for the pc7448. 5.1 detailed specification this specification describes the sp ecific requirements for the microprocessor pc7448 in compliance with e2v standard screening. 5.2 applicable documents 1. mil-std-883: test methods and procedures for electronics. the microcircuits are in accordance with the applicable documents and as specified herein. table 4-1. device parameters parameter description technology 90 nm cmos soi, nine-layer metal die size 8 mm 7.3 mm transistor count 90 million logic design mixed static and dynamic packages surface mount 360 ceramic ball grid array (hitce) surface mount 360 ceramic land grid array (hitce) rohs hitce lga surface mount 360 ceramic ball grid array with lead-free spheres (hitce) = rohs core power supply 1.1v 50 mv (1250 mhz) 1.05v 50 mv (1267 mhz) 1.0v 50 mv (600 mhz, 1000 mhz) i/o power supply 1.5v 5% dc, or 1.8v 5% dc, or 2.5v 5% dc
11 0814g?hirel?04/09 e2v semiconductors sas 2009 pc7448 5.3 dc electrical characteristics the tables in this section describe the pc7448 dc electrical characteristics. table 5-1 provides the absolute maximum ratings. notes: 1. functional and tested operating conditions are given in table 5-3 on page 12 . absolute maximum ratings are stress ratings only and functional operation at the maximums is not guaranteed. stresses beyond t hose listed may affect device reliability or cause permanent damage to the device. 2. see section 9.2 ?power supply design and sequencing? on page 35 for power sequencing requirements. 3. bus must be configured in the corresponding i/o voltage mode; see table 5-2 on page 12 . 4. caution : v in must not v in ov dd by more than 0.3v at any time including du ring power-on reset except as allowed by the overshoot specifications. v in may overshoot/undershoot to a voltage and for a maximum duration as shown in figure 5-1 . figure 5-1 shows the undershoot and overshoot voltage on the pc7448. figure 5-1. overshoot/undershoot voltage the pc7448 provides several i/o vo ltages to support both compatibility with existi ng systems and migra- tion to future systems. the pc7448 core voltage must always be provided at the nominal voltage (see table 5-3 on page 12 ) or at the supported derated voltage (see section ?? on page 23 ). table 5-1. absolute maximum ratings (1) characteristic symbol maximum value unit notes core supply voltage v dd -0.3 to 1.4 v (2) pll supply voltage av dd -0.3 to 1.4 v (2) processor bus supply voltage i/o voltage mode = 1.5v ov dd -0.3 to 1.8 v (3) i/o voltage mode = 1.8v -0.3 to 2.2 (3) i/o voltage mode = 2.5v -0.3 to 3.0 (3) input voltage processor bus v in -0.3 to ov dd + 0.3 v (4) jtag signals v in -0.3 to ov dd + 0.3 v storage temperature range t stg ?65 to 150 c gnd gnd ? 0.3v gnd ? 0.7v not to exceed 10% of t sys ov dd + 20% ov dd + 5% ov dd (1) v ih v il
12 0814g?hirel?04/09 pc7448 e2v semiconductors sas 2009 the input voltage threshold for each bus is selected by sampling the state of the voltage select pins at the negation of the signal hreset . the output voltage will swing from gnd to the maximum voltage applied to the ov dd power pins. table 5-2 on page 12 provides the input threshold voltage settin gs. because these settings may change in future products, it is re commended that bvsel[0:1] be configured using resist or options, jumpers, or some other flexible means, with the ca pability to reconfigure the termination of this signal in the future, if necessary. notes: 1. caution: the i/o voltage mode selected must agree with the ov dd voltages supplied. see table 5-3 . 2. if used, pull-down resistors should be less than 250 . 3. the pin configuration used to sele ct 1.8v mode on the pc7448 is not compatible with the pin configura- tion used to select 1.8v mode on the pc7447a and earlier devices. 4. the pin configuration used to sele ct 2.5v mode on the pc7448 is fu lly compatible with the pin configu- ration used to select 2.5v mode on the pc7447a and earlier devices. table 5-3 provides the recommended operating conditions for the pc7448 part numbers described by this document. note: table 5-3 describes the nominal operating conditions of the device. for information regarding the operation of the device at supported derated core voltage conditions, see section ?? on page 23 . notes: 1. these are the recommended and tested operating conditions. in addition, these devices also support voltage derating; se e section ?? on page 23 . proper device operation outside of th ese conditions and those specified in section on page 23 is not guaranteed. 2. this voltage is the input to the filter discussed in section 9.2.2 ?pll power s upply filtering? on page 36 and not necessarily the voltage at the av dd pin, which may be reduced from v dd by the filter. table 5-2. input threshold voltage setting bvsel0 bvsel1 i/o voltage mode (1) notes 0 0 1.8v (2)(3) 0 1 2.5v (2)(4) 1 0 1.5v (2) 1 1 2.5v (4) table 5-3. recommended operating conditions (1) characteristic symbol recommended value unit notes 600 mhz, 1000 mhz 1250 mhz 1267 mhz min max min max min max core supply voltage v dd 1.0v 50 mv 1.1v 50 mv 1.05v 50 mv v (3) pll supply voltage av dd 1.0v 50 mv 1.1v 50 mv 1.05v 50 mv v (2)(3) processor bus supply voltage i/o voltage mode = 1.5v ov dd 1.5v 5% v (4) i/o voltage mode = 1.8v 1.8v 5% (4) i/o voltage mode = 2.5v 2.5v 5% (4) input voltage processor bus v in gnd ov dd gnd ov dd gnd ov dd v jtag signals v in gnd ov dd gnd ov dd gnd ov dd operating temperature t j t c = ? 55 t j = +125 t c = ?55 t j = +125 t c = ?55 t j = +125 c
13 0814g?hirel?04/09 e2v semiconductors sas 2009 pc7448 3. v dd and av dd may be reduced in order to reduce power consumption if further maximum core frequency constraints are observed. see section ?? on page 23 , for specific information. 4. caution: power sequencing requirements must be met; see section 9.2 ?power supply design and sequencing? on page 35 . 5. see section 9.2.3 ?transient specifications? on page 37 for information regarding transients on this power supply. table 5-4 provides the package thermal characteristics for the pc7448. for more information regarding thermal management, see section 9.8, ?thermal management information.? notes: 1. refer to section 9.8, ?thermal management information,? for details about thermal management. 2. junction temperature is a function of on -chip power dissipation, package thermal resistance, mounting site (board) tempera- ture, ambient temperature, airflow, power dissipation of other components on the board, and board thermal resistance. 3. per jedec jesd51-2 with the single-layer board horizontal. 4. per jedec jesd51-6 with the board horizontal. 5. thermal resistance between the die and the printed-circuit board per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. 6. this is the thermal resistance between die and case top su rface as measured by the cold plate method (mil spec-883 method 1012.1) with the calculated case temperature. the actual value of r jc for the part is less than 0.1 c/w. table 5-4. package thermal characteristics (1) characteristic symbol value unit notes junction-to-ambient thermal resistance, natural convection, single-layer (1s) board r ja 26 c/w (2)(3) junction-to-ambient thermal resistance, natural convection, four-layer (2s2p) board r jma 19 c/w (2)(4) junction-to-ambient thermal resistance, 200 ft ./min. airflow, single-layer (1s) board r jma 22 c/w (2)(4) junction-to-ambient thermal resistance, 200 ft./min. airflow, four-layer (2s2p) board r jma 16 c/w (2)(4) junction-to-board thermal resistance r jb 11 c/w (5) junction-to-case th ermal resistance r jc < 0.1 c/w (6)
14 0814g?hirel?04/09 pc7448 e2v semiconductors sas 2009 table 5-5 provides the dc electrical characteristics for the pc7448. notes: 1. nominal voltages; see table 5-3 for recommended operating conditions. 2. all i/o signals are referenced to ov dd . 3. excludes test signals and ieee 1149.1 boundary scan (jtag) signals. 4. the leakage is measured for nominal ov dd /gv dd and v dd , or both ov dd /gv dd and v dd must vary in the same direction (for example, both ov dd and v dd vary by either +5% or ?5%). 5. capacitance is periodically sampled rather than 100% tested. table 5-5. dc electrical specifications (at recommended oper ating conditions , see table 5-3 on page 12 ) characteristic nominal bus voltage (1) symbol min max unit notes input high voltage (all inputs) 1.5 v ih ov dd 0.65 ov dd + 0.3 v (2) 1.8 ov dd 0.65 ov dd + 0.3 2.5 1.7 ov dd + 0.3 input low voltage (all inputs) 1.5 v il -0.3 ov dd 0.35 v (2) 1.8 -0.3 ov dd 0.35 2.5 -0.3 0.7 input leakage current, v in = gv dd /o dd v in = gnd ?i in ?50 ?50 a (2)(3) high-impedance (off-state) leakage current, v in = gv dd /o dd v in = gnd ?i tsi ?50 ?50 a (2)(3)(4) output high voltage at i oh = ?5 ma 1.5 v oh ov dd - 0.45 ? v 1.8 ov dd - 0.45 ? 2.5 1.8 ? output low voltage at i ol = 5 ma 1.5 v ol ?0.45 v 1.8 ? 0.45 2.5 ? 0.6 capacitance, v in = 0v, f = 1 mhz all inputs c in ?8pf (5)
15 0814g?hirel?04/09 e2v semiconductors sas 2009 pc7448 table 5-6 on page 15 provides the power consumption for the pc7448 part numbers described by this document; see section 10. ?ordering information? on page 52 , for more information. for information regarding power consumption when dynamic frequency switching is enabled, see section 9.7.5 ?dynamic frequency switching (dfs)? on page 49 . note: the power consumption information in this table a pplies when the device is operated at the nominal core voltage indicated in table 5-6 . for power consumption at derated core voltage conditions, see section ?? on page 23 . notes: 1. these values specify the power consumption for the core power supply (v dd ) at nominal voltage and apply to all valid pro- cessor bus frequencies and configurations. the values do not include i/o supply power (ov dd ) or pll supply power (av dd ). ov dd power is system dependent but is typically < 5% of v dd power. worst case power consumption for av dd < 13 mw. 2. typical power is an average value measured at the nominal recommended v dd (see table 5-3 on page 12 ) and 65 c while running the dhrystone 2.1 benchmark a nd achieving 2.3 dhrystone mips/mhz. 3. maximum power is the average measured at nominal v dd and 125 c junction temperature while running an entirely cache- resident, contrived sequence of instructions which keep all the execution units maximally busy. 4. doze mode is not a user-definable state; it is an intermed iate state between full-power and ei ther nap or sleep mode. as a result, power consumption for this mode is not tested. 5. typical thermal power consumption is an average value measured at the nominal recommended v dd (see table 5-3 on page 12 ) and 105 c while running the dhrystone 2.1 benchmark and ac hieving 2.3 dhrystone mi ps/mhz. this parameter is not 100% tested but periodically sampled. 6. typical power consumption for these modes is measured at the nominal recommended v dd (see table 5-3 on page 12 ) and 105 c in the mode described. this parameter is not 100% tested but is periodically sampled. 7. power consumption for the 600 mhz k-spec and 1267 mhz n- spec devices are intentionally constrained via testing and sorting to assure low power consumption for this device. table 5-6. power consumption for pc7448 processor (cpu) frequency unit notes 600 mhz 1000 mhz 1250 mhz 1267 mhz (7) full-power mode ty p i c a l n-spec: 8.5 k-spec (7) : 6.5 9.5 10 8.4 w (1)(2) typical thermal n-spec: 10.8 k-spec (7) : 7.5 12 12.6 10.3 w (1)(5) maximum n-spec: 12.5 k-spec (7) : 8.5 13.9 14.6 t j = 110 c : 12w t j = 125 c : 13w w (1)(3) nap mode typical 6.5 6.5 8.3 6.5 w (1)(6) sleep mode typical 6.3 6.3 8 6.3 w (1)(6) deep sleep mode (pll disabled) typical 6 6 7.7 6.0 w (1)(6)
16 0814g?hirel?04/09 pc7448 e2v semiconductors sas 2009 5.4 voltage and frequency derating to reduce the power consumption of the device, these devices support voltage and frequency derating whereby the core voltage (v dd ) may be reduced if the reduced maximum processor core frequency requirements are observed. the supported derated core voltage, resulting maximum processor core fre- quency (f core ), and power consumption are provided in table 5-7 . only those parameters in table 5-7 are affected; all other parameter specifications are unaffected. 5.5 ac electrical characteristics this section provides the ac electrical characteristic s for the pc7448. after fabrication, functional parts are sorted by maximum processor core frequency as shown in ?clock ac specifications? , and tested for conformance to the ac specifications for that frequency. the processor core frequency, determined by the bus (sysclk) frequency and the settings of the pll_cfg[0:5] signals, can be dynamically modified using dynamic frequency switching (dfs). parts ar e sold by maximum processor core frequency.see section 9.7.5 ?dynamic frequency switching (dfs)? on page 49 . 5.5.1 clock ac specifications table 5-8 on page 16 provides the clock ac timing specifications for the pc7448 part numbers described herein. note: the core frequency information in this table applie s when the device is operated at the nominal core volt- age indicated in table 5-3 on page 12 . for core frequency specifications at derated core voltage conditions, see section ?? on page 23 . table 5-7. supported voltage, core frequency, and power consumption derating maximum rated core frequency (device marking) supported derated core voltage (v dd ) maximum derated core frequency (f core ) full-power mode power consumption typical thermal maximum 600 na 1000 na 1250 na 1267 1.0v 50 mv 1000 mhz 6.0w 7.3w t j = 110 c : 8.5w t j = 125 c : 9.5w table 5-8. clock ac timing specifications (a t recommended operating conditions , see table 5-3 on page 12 ) characteristic symbol maximum processor core frequency unit notes 600 mhz 1000 mhz 1250 mhz 1267 mhz min max min max min max min max processor frequency dfs mode disabled f core 500 600 500 1000 500 1250 500 1267 mhz (1)(8)(9) dfs mode enabled f core-dfs 250 300 250 500 250 625 250 633 (10) vco frequency f vco 500 600 500 1000 500 1250 500 1267 mhz (1)(9) sysclk frequency f sysclk 33 200 33 200 33 200 33 200 mhz (1)(2)(8) sysck cycle time t sysclk 530530530530ns (2) sysclk rise and fall time t kr , t kf ? 0.5 ? 0.5 ? 0.5 ? 0.5 ns (3) sysclk duty cycle measured at ov dd /2 t khkl /t sysclk 40 60 40 60 40 60 40 60 % (4) sysclk cycle-to-cycle jitter ? 150 ? 150 ? 150 ? 150 ps (5)(6)
17 0814g?hirel?04/09 e2v semiconductors sas 2009 pc7448 notes: 1. caution: the sysclk frequency and p ll_cfg[0:5] se ttings must be chosen such th at the resulting sysclk (bus) fre- quency, processor core frequency, and pll (vco) frequency do not exceed their respective maximum or minimum operating frequencies. refer to the pll_cfg[0:5] signal description in section 9.1.1 ?pll configuration? on page 32 , for valid pll_cfg[0:5] settings. 2. actual maximum system bus frequency is system-dependent. see section 5.5.1 ?clock ac specifications? on page 16 . 3. rise and fall times for the sysclk input measured from 0.4 to 1.4v. 4. timing is guaranteed by design and characterization. 5. guaranteed by design. 6. the sysclk driver?s closed loop jitter bandwidth should be less than 1.5 mhz at ? 3 db. 7. relock timing is guaranteed by design and characterization. pll-relock time is the maximum amount of time required for pll lock after a stable v dd and sysclk are reached during the power-on reset sequence. this specification also applies when the pll has been disabled and subsequently re-enabled during sleep mode. also note that hreset must be held asserted for a minimum of 255 bus clocks after the pll-relock time during the power-on reset sequence. 8. this reflects the maximum and minimum core frequencies when the dynamic frequency swit ching feature (dfs) is dis- abled. f core_dfs provides the maximum and minimum core frequencies when operating in a dfs mode. 9. caution : these values specify the maximum processor core and vco frequencies when the device is operated at the nomi- nal core voltage. if operating the device at the derated core voltage, the processor core and vco frequencies must be reduced. see section ?? on page 23 , for more information. 10. this specification is provided to support use of the dynam ic frequency switching (dfs) feature and is applicable only when one of the dfs modes (divide-by-2 or divide-by-4) has been enabled. when dfs is disabled, the core frequency must con- form to the maximum and minimum frequencies stated for f core . 11. use of the dfs feature does not affect vco frequency. figure 5-2 provides the sysclk input timing diagram. figure 5-2. sysclk input timing diagram note: v m = midpoint voltage (ov dd /2) sysclk vm vm vm t khkl t sysclk cv il c v ih t kr t kf
18 0814g?hirel?04/09 pc7448 e2v semiconductors sas 2009 5.5.2 processor bus ac specifications table 5-9 provides the processor bus ac timing specifications for the pc7448 as defined in figure 5-3 on page 19 and figure 5-4 on page 19 .. notes: 1. all input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge of the input sysclk. all output specifications are m easured from the midpoint of the rising edge of sysclk to the midpoint of the sig- nal in question. all output timings assume a purely resistive 50 load (see figure 5-3 on page 19 ). input and output timings are measured at the pin; time-of-fli ght delays must be added for trace lengths, vias, and connecto rs in the system. table 5-9. processor bus ac timing specifications (1) (at recommended operating conditions, see table 5-3 on page 12 ) parameter symbol (2) all speed grades unit notes min max input setup times: a[0:35], ap[0:4] d[0:63], dp[0:7] aack , artry , bg , ckstp_in , dbg , dti[0:3], gbl , tt[0:3], qack , ta , tben, tea , ts ,ext_qual, pmon_in , shd [0:1], bmode [0:1], bvsel[0:1] t avkh t dvkh t ivkh t mvkh 1.5 1.5 1.5 1.5 ? ? ? ? ns ? ? ? (8) input hold times: a[0:35], ap[0:4] d[0:63], dp[0:7] aack , artry , bg , ckstp_in , dbg , dti[0:3], gbl , tt[0:3], qack , ta , tben, tea , ts , ext_qual, pmon_in , shd [0:1] bmode [0:1], bvsel[0:1] t axkh t dxkh t ixkh t mxkh 0 0 0 0 ? ? ? ? ns ? ? ? (8) output valid times: a[0:35], ap[0:4] d[0:63], dp[0:7] aack , br , ci , ckstp_in , drdy , dti[0:3], gbl , hit , pmon_out , qreq, tbst , tsiz[0:2], tt[0:3], wt ts artry , shd [0:1] t khav t khdv t khov t khtsv t kharv ? ? ? ? ? 1.8 1.8 1.8 1.8 1.8 ns output hold times: a[0:35], ap[0:4] d[0:63], dp[0:7] aack , br , ci , ckstp_in , drdy , dti[0:3], gbl , hit , pmon_out , qreq, tbst , tsiz[0:2], tt[0:3], wt ts , artry , shd [0:1] t khax t khdx t khox t khtsx t kharx 0.5 0.5 0.5 0.5 0.5 ? ? ? ? ? ns sysclk to output enable t khoe 0.5 ? ns (5) sysclk to output high impedance (all except ts , artry , shd0 , shd1 )t khoz ?1.8ns (5) sysclk to ts high impedance after precharge t khtspz ?1t sysclk (3)(4)(5) maximum delay to artry /shd0 /shd1 precharge t kharp ?1t sysclk (3)(5)(6)(7) sysclk to artry /shd0 /shd1 high impedance after precharge t kharpz ?2t sysclk (3)(5)(6)(7)
19 0814g?hirel?04/09 e2v semiconductors sas 2009 pc7448 2. the symbology used for timing specificat ions herein follows the pattern of t (signal)(state)(reference)(state) for inputs and t (refer- ence)(state)(signal)(state) for outputs. for example, t ivkh symbolizes the time input signals (i) reach the valid state (v) relative to the sysclk reference (k) going to the high (h) state or input setup time. and t khov symbolizes the time from sysclk(k) going high (h) until outputs (o) are valid (v) or output valid time. in put hold time can be read as the time that the input signal (i ) went invalid (x) with respect to the rising clock edge (kh) (not e the position of the reference and its state for inputs) and o ut- put hold time can be read as the time from the ri sing edge (kh) until the output went invalid (ox). 3. t sysclk is the period of the external clock ( sysclk) in ns. the numbers given in the ta ble must be multiplied by the period of sysclk to compute the actual time duration (in ns) of the parameter in question. 4. according to the bus protocol, ts is driven only by the currently active bus master. it is asserted low and precharged high before returning to high impedance, as shown in figure 5-5 on page 20 . the nominal precharge width for ts is t sysclk , that is, one clock period. since no master can assert ts on the following clock edge, there is no concern regarding contention with the precharge. output valid and output hold timing is tested for the signal asserted. output valid time is tested for pre- charge.the high-impedance behavior is guaranteed by design. 5. guaranteed by design and not tested. 6. according to the bus protocol, artry can be driven by multiple bus masters through the clock period immediately following aack . bus contention is not an issue because any master asserting artry will be driving it low. any master asserting it low in the first clock following aack will then go to high impedance for a fraction of a cycle, then negated fo r up to an entire cycle (crossing a bus cycle boundary) before being three-stat ed again. the nominal precharge width for artry is 1.0 t sysclk ; that is, it should be high impedance as shown in figure 5-5 before the first opportunity for another master to assert artry . out- put valid and output hold timing is tested for the signal asserted.the high-impedance behavior is guaranteed by design. 7. according to the mpx bus protocol, shd0 and shd1 can be driven by multiple bus ma sters beginning tw o cycles after ts . timing is the same as artry , that is, the signal is high impedance for a frac tion of a cycle, then negated for up to an entire cycle (crossing a bus cycle boundary) before being th ree-stated again. the nominal precharge width for shd0 and shd1 is 1.0 t sysclk . the edges of the precharge vary depending on the programmed ratio of core to bus (pll configurations). 8. bmode [0:1] and bvsel[0:1] are mo de-select inputs. bmode [0:1] are sampled before and after hreset negation. bvsel[0:1] are sa mpled before hreset negation. these parameters represent the input setup and hold times for each sample. these values are guaranteed by design and not tested. bmode [0:1] must remain stable after the second sample; bvsel[0:1] must remain stable after the first (and only) sample. see figure 5-4 on page 19 for sample timing. figure 5-6 provides the ac test load for pc7448. figure 5-3. ac test load figure 5-4 provides the bmode[0:1] input timing diagram for the pc7448. these mode select inputs are sampled once before and once after hreset negation. figure 5-4. bmode[0:1] input sample timing diagram note: v m = midpoint voltage (ov dd /2) output z 0 = 50 r l = 50 ov dd /2 hreset bmode[0:1] v m v m sysclk 1st sample 2nd sample
20 0814g?hirel?04/09 pc7448 e2v semiconductors sas 2009 figure 5-5 provides the input/output timing diagram for the pc7448. figure 5-5. input/output timing diagram note: vm = midpoint voltage (ov dd /2) sysclk all inputs vm all outputs vm (except ts, all outputs ts vm t khoe artry, shd0, shd1) (except ts, artry, shd0, shd1) artry, shd0, shd1 t avkh t khav t mvkh t ivkh t axkh t ixkh t mxkh t khdv t khov t khax t khdx t khox t khoz t khtspz t khtsx t khtsv t khtsv t kharv t kharp t kharx t kharpz
21 0814g?hirel?04/09 e2v semiconductors sas 2009 pc7448 5.5.3 ieee 1149.1 ac timing specifications table 5-10 provides the ieee 114 9.1 (jtag) ac timing specif ications as defined in figure 5-7 on page 22 through figure 5-10 on page 23 . notes: 1. all outputs are measured from the midpoint volta ge of the falling/rising edge of tclk to the midpoint of the signal in question. the output timings are measur ed at the pins. all output timings assume a purely resistive 50 load (see figure 5-6 ). time-of-flight delays must be added for trace lengths, vias and con- nectors in the system. 2. trst is an asynchronous level sensitive signal. the time is for test purposes only. 3. non-jtag signal input ti ming with respect to tck. 4. non-jtag signal output timing with respect to tck. 5. guaranteed by design and characterization. figure 5-6 provides the ac test load for tdo and the boundary-scan outputs of the pc7448. figure 5-6. alternate ac test load for the jtag interface table 5-10. jtag ac timing specificatio ns (independent of sysclk) (1) (at recommended operating conditions, see table 5-3 on page 12 ) parameter symbol min max unit notes tck frequency of operation f tclk 0 33.3 mhz tck cycle time t tclk 30 ? ns tck clock pulse width measured at 1.4v t jhjl 15 ? ns tck rise and fall times t jr and t jf ?2ns trst assert time t trst 25 ? ns (2) input setup times: - boundary-scan data - tms, tdi t dvjh t ivjh 4 0 ? ? ns (3) input hold times: - boundary-scan data - tms, tdi t dxjh t ixjh 20 25 ? ? ns (3) valid times: - boundary-scan data - tdo t jldv t jlov 4 4 20 25 ns (4) output hold times: - boundary-scan data - tdo t jldx t jlox 30 30 ? ? ns (4) tck to output high impedance: - boundary-scan data - tdo t jldz t jloz 3 3 19 9 ns (4)(5) output z 0 = 50 r l = 50 ov dd /2
22 0814g?hirel?04/09 pc7448 e2v semiconductors sas 2009 figure 5-7 provides the jtag clock input timing diagram. figure 5-7. jtag clock input timing diagram note: vm = midpoint voltage (ov dd /2) figure 5-8 provides the trst timing diagram. figure 5-8. trst timing diagram note: vm = midpoint voltage (ov dd /2) figure 5-9 provides the boundary-scan timing diagram. figure 5-9. boundary-scan timing diagram note: vm = midpoint voltage (ov dd /2) vm vm vm t tclk t jr t jf t jhjl tclk vm tck boundary data inputs boundary data outputs boundary data outputs t dxjh t dvjh t jldv t jldz output data valid t jldx vm input data valid output data valid vm tck boundary data inputs boundary data outputs boundary data outputs t dxjh t dvjh t jldv t jldz output data valid t jldx vm input data valid output data valid
23 0814g?hirel?04/09 e2v semiconductors sas 2009 pc7448 figure 5-10 provides the test access port timing diagram. figure 5-10. test access port timing diagram note: vm = midpoint voltage (ov dd /2) t jlox input data valid t ivjh t ixjh t jlov t jloz output data valid output data valid vm tck tdi, tms tdo tdo vm
24 0814g?hirel?04/09 pc7448 e2v semiconductors sas 2009 6. pin assignments figure 6-1 shows the pinout of the pc7448, 360 high coefficient of the thermal expansion ceramic ball grid array (hitce) package as viewed from the top surface. figure 6-2 shows the side profile of the hitce package to indicate the direction of the top surface view. figure 6-1. pinout of the pc7448, 360 hitce package as viewed from the top surface figure 6-2. pinout of the pc7448, 360 hitce package as viewed from the top surface a b c d e f g h j k l m n p r t 3 2 1456 16 17 18 19 u v w 15 14 13 12 11 10 9 8 7 not to scale substrate assembly encapsulant view die
25 0814g?hirel?04/09 e2v semiconductors sas 2009 pc7448 7. pinout listings table 7-1 provides the pinout listing for the pc7448, 360 hitce package. the pinouts of the pc7448 and pc7447a are pin compatible, but the requirem ents regarding the use of the additional power and ground pins may change. the pc7448 may require these pins be connected to the appropriate power or ground plane to achieve the full rated core frequency. as a result, these pins should be connected in all new designs. additionally, the pc7448 may be populated on a board designed for a pc7447 (or pc7445 or pc7441), provided the core voltage can be made to match the requirements in table 5-3 and all pins defined as ?no connect? for the pc7447 are unterminated, as required by the pc7457 risc microprocessor hard- ware specifications. the pc7448 us es pins previously marked ?no connect? for the temperature diode pins and for additional power and ground connec tions. the additional power and ground pins are required to achieve high core frequencies; see section 9.3 ?connection recommendations? on page 38 , for additional information. because these ?no c onnect? pins in the pc7447 360 pin package are not driven in functional mode, an pc7447 can be populated in an pc7448 board. note: caution must be exercised when performing boundary scan test operations on a board designed for an pc7448, but populated with an pc7447 or earlier device. this is because in the pc7447 it is possible to drive the latches associated with the former ?no connect? pins in the pc7447, pote ntially causing contention on those pins. to prevent this, ensur e that these pins are not connect ed on the board or, if they are con- nected, ensure that the stat es of internal pc7447 latches do not cause these pins to be driven during board testing. for the pc7448, pins that were defined as the test[0:4] factory test signal group on the pc7447a and earlier devices have been assigned new functions. for most of these, the termination recommendations for the test[0:4] pins of the pc7447a are compatible with the pc7448 and will allow correct operation with no performance loss. the exception is bv sel1 (test3 on the pc7447a and earlier devices), which may require a different termination depending which i/o voltage mode is desired; see table 5-2 on page 12 for more information. note: this pinout is not compatible with th e pc750, pc7400, or pc7410 360 bga package. table 7-1. pinout listing for the pc7448, 360 hitce package signal name pin number active i/o notes a[0:35] e11, h1, c11, g3, f10, l2, d11, d1, c10, g2, d12, l3, g4, t2, f4, v1, j4, r2, k5, w2, j2, k4, n4, j3, m5, p5, n3, t1, v2, u1, n5, w1, b12, c4, g10, b11 high i/o (2) aack r1 low input ap[0:4] c1, e3, h6, f5, g7 high i/o (2) artry n2 low i/o (3) av dd a8 ? input bg m1 low input bmode0 g9 low input (4) bmode1 f8 low input (5) br d2 low output bvsel0 b7 high input (1)(6) bvsel1 e10 high input (1)(20) ci j1 low output ckstp_in a3 low input
26 0814g?hirel?04/09 pc7448 e2v semiconductors sas 2009 ckstp_out b1 low output clk_out h2 high output d[0:63] r15, w15, t14, v16, w16, t15, u15, p14, v13, w13, t13, p13, u14, w14, r12, t12, w12, v12, n11, n10, r11, u11, w11, t11, r10, n9, p10, u10, r9, w10, u9, v9, w5, u6, t5, u5, w7, r6, p7, v6, p17, r19, v18, r18, v19, t19, u19, w19, u18, w17, w18, t16, t18, t17, w3, v17, u4, u8, u7, r7, p6, r8, w8, t8 high i/o dbg m2 low input dfs2 a12 low input (20)(21) dfs4 b6 low input (12)(20)(21) dp[0:7] t3, w4, t4, w9, m6, v3, n8, w6 high i/o drdy r3 low output (7) dti[0:3] g1, k1, p1, n1 high input (8) ext_qual a11 high input (9) gbl e2 low i/o gnd b5, c3, d6, d13, e17, f3, g17, h4, h7, h9, h11, h13, j6, j8, j10, j12, k7, k3, k9, k11, k13, l6, l8, l10, l12, m4, m7, m9, m11, m13, n7, p3, p9, p12, r5, r14, r17, t7, t10, u3, u13, u17, v5, v8, v11, v15 ?? gnd a17, a19, b13, b16, b18, e12, e19, f13, f16, f18, g19, h18, j14, l14, m15, m17, m19, n14, n16, p15, p19 ?? (15) gnd_sense g12, n13 ?? (19) hit b2 low output (7) hreset d8 low input int d4 low input l1_tstclk g8 high input (9) l2_tstclk b3 high input (10) lv r a m b10 ?? (12)(20)(22) nc (no connect) a6, a14, a15, b14, b15, c14, c15, c16, c17, c18, c19, d14, d15, d16, d17, d18, d19, e14, e15, f14, f15, g14, g15, h15, h16, j15, j16, j17, j18, j19, k15, k16, k17, k18, k19, l15, l16, l17, l18, l19 ?? (11) lssd_mode e8 low input (6)(12) mcp c9 low input ov dd b4, c2, c12, d5, f2, h3, j5, k2, l5, m3, n6, p2, p8, p11, r4, r13, r16, t6, t9, u2, u12, u16, v4, v7, v10, v14 ?? ov dd _sense e18, g18 ?? (16) pll_cfg[0:4] b8, c8, c7, d7, a7 high input pll_cfg[5] d10 high input (9)(20) pmon_in d9 low input (13) pmon_out a9 low output qack g5 low input qreq p4 low output shd [0:1] e4, h5 low i/o (3) table 7-1. pinout listing for the pc7448, 360 hitce package (continued) signal name pin number active i/o notes
27 0814g?hirel?04/09 e2v semiconductors sas 2009 pc7448 notes: 1. ov dd supplies power to the processor bus, jtag, and all control signals; v dd supplies power to the processor core and the pll (after filtering to become av dd ). to program the i/o voltage, see table 5-2 on page 12 . if used, the pull-down resistor should be less than 250 because these settings may change in future pr oducts, it is recommended bvsel[0:1] be config- ured using resistor options, jumpers, or some other flexible means, with the capability to reconf igure the termination of this signal in the future if necessary. for actual recommended value of v in or supply voltages see table 5-3 on page 12 . 2. unused address pins must be pulled down to gnd and corresponding address parity pins pulled up to ov dd . 3. these pins require weak pull-up resistors (for example, 4.7 k ) to maintain the control signals in the negated state after they have been actively negated and released by the pc7448 and other bus masters. 4. this signal selects between mpx bus mode (asserted) and 60x bus mode (negated) and will be sampled at hreset going high. 5. this signal must be negated during reset, by pull-up resistor to ov dd or negation by ?hreset (inverse of hreset ), to ensure proper operation. 6. internal pull up on die. 7. ignored in 60x bus mode. 8. these signals must be pulled down to gnd if unused, or if the pc7448 is in 60x bus mode. 9. these input signals are for factory use only and must be pulled down to gnd for normal machine operation. 10. this test signal is recommended to be tied to hreset ; however, other configurations will not adversely affect performance. 11. these signals are for factory use only and must be left unc onnected for normal machine operation. some pins that were ncs on the pc7447 have now been defined for other purposes. 12. these input signals are for factory use only and must be pulled up to ov dd for normal machine operation. smi f9 low input sreset a2 low input sysclk a10 ? input ta k6 low input tben e1 high input tbst f11 low output tck c6 high input tdi b9 high input (6) tdo a4 high output tea l1 low input temp_anode n18 ?? (17) temp_cathode n19 ?? (17) tms f1 high input (6) trst a5 low input (6)(14) ts l4 low i/o (3) tsiz[0:2] g6, f7, e7 high output tt[0:4] e5, e6, f6, e9, c5 high i/o wt d3 low output v dd h8, h10, h12, j7, j9, j11, j13, k8, k10, k12, k14, l7, l9, l11, l13, m8, m10, m12 ? ? v dd a13, a16, a18, b17, b19, c13, e13, e16, f12, f17, f19, g11, g16, h14, h17, h19, m14, m16, m18, n15, n17, p16, p18 ?? (15) v dd _sense g13, n12 ?? (18) table 7-1. pinout listing for the pc7448, 360 hitce package (continued) signal name pin number active i/o notes
28 0814g?hirel?04/09 pc7448 e2v semiconductors sas 2009 13. this pin can externally cause a performance monitor event. counting of the event is enabled through software. 14. this signal must be asserted during reset, by pull down to gnd or assertion by hreset , to ensure proper operation. 15. these pins were ncs on the pc7447. see section 9.3 ?connection recommendations? on page 38 , for more information. 16. these pins were ov dd pins on the pc7447. these pins are internally connected to ov dd and are intended to allow an exter- nal device to detect the i/o voltage level present inside the device package. if unused, they must be connected directly to ov dd or left unconnected. 17. these pins provide connectivity to the on-chip temperature diode that can be used to determine the die junction temperature of the processor. these pins may be left unterminated if unused. 18. these pins are internally connected to v dd and are intended to allow an external device to detect the processor core voltage level present inside the device package. if unused, they must be connected directly to v dd or left unconnected. 19. these pins are internally connected to gnd and are intended to allow an external device to detect the processor ground voltage level present inside the device package. if unused, th ey must be connected directly to gnd or left unconnected. 20. these pins were in the test[0:4] factory test pin group on the pc7447a and pc7447. they have been assigned new func- tions on the pc7448. 21. these pins can be used to enable the supported dynamic fr equency switching (dfs) modes via hardware. if both are pulled down, dfs mode is disabled completely and cannot be enabled via software. if unused, they should be pulled up to ov dd to allow software control of dfs. see the pc7450 risc micr oprocessor family reference manual for more information. 22. this pin is provided to allow operation of the l2 cache at lo w core voltages and is for factory use only. see the pc7450 ris c microprocessor family reference manual for more information. 8. package description the following sections provide the package parameters and mechanical dimensions for the hitce package. 8.1 package parameters fo r the pc7448, 360 hitce bga the package parameters are as provided in the following list. the package type is 25 25 mm, 360-lead high coefficient of thermal expansion ceramic ball grid array (hitce). package outline 25 mm 25 mm interconnects 360 (19 19 ball array - 1) pitch 1.27 mm (50 mil) minimum module height 2.32 mm maximum module height 2.80 mm ball diameter 0.89 mm (35 mil) coefficient of thermal expansion 12.3 ppm/ c
29 0814g?hirel?04/09 e2v semiconductors sas 2009 pc7448 8.2 mechanical dimensions for the pc7448, 360 hitce bga figure 8-1 on page 29 provides the mechanical dimensions and bottom surface nomenclature for the pc7448, 360 hitce bga package. figure 8-1. mechanical dimensions and bottom surface nomenclature for the pc7448, 360 hitce bga package 8.3 package parameters fo r the pc7448, 360 hitce lga the package parameters are as provided in the follo wing list. the package type is 25 25 mm, 360 pin high coefficient of thermal expansion ceramic land grid array (hitce). package outline 25 mm 25 mm interconnects 360 (19 19 ball array - 1) pitch 1.27 mm (50 mil) minimum module height 1.52 mm maximum module height 1.80 mm pad diameter 0.89 mm (35 mil) coefficient of thermal expansion 12.3 ppm/ c c a 360x b 0.3 a 0.15 b 0.2 2x a1 corner capacitor region 0.35 a millimeters dim min max a 2.32 2.80 a1 0.80 1 a2 0.70 0. 9 0 a3 ? 0.6 b 0.82 0. 9 3 d 25 bsc d1 ? 11.3 d2 8 ? d3 ? 6.5 d4 7.2 7.4 e 1.27 bsc e 25 bsc e1 ? 11.3 e2 8 ? e3 ? 6.5 e4 7. 9 8.1 d e e 0.2 2x c b a b c d e f g h j k l m n p r t a u w v 1 d3 e2 e1 a a1 a2 a3 e4 d4 e3 d1 d2 1 2 345 6 78 9 10 11 12 13 14 15 16 17 18 1 9 0.15 a notes: 1. dimensioning and tolerance per asme y14.5m, 1 99 4. 2. dimensions in millimeters. 3. top side a1 corner index is a metalized feature with various shapes. bottom side a1 corner is designated with a ball missing from the array.
30 0814g?hirel?04/09 pc7448 e2v semiconductors sas 2009 8.4 mechanical dimensions for the pc7448, 360 hitce lga figure 8-1 provides the mechanical dimensions and bot tom surface nomenclature for the pc7448, 360 hitce lga package. figure 8-2. mechanical dimensions and bottom surface nomenclature for the pc7448, 360 hitce lga package 8.5 package parameters for the pc7 448, 360 hitce rohs-compliant bga the package parameters are as provided in the following list. the package type is 25 25 mm, 360-lead high coefficient of thermal expansion ceramic ball grid array (hitce) with rohs-compliant lead-free spheres. package outline 25 mm 25 mm interconnects 360 (19 19 ball array - 1) pitch 1.27 mm (50 mil) minimum module height 1.92 mm maximum module height 2.40 mm ball diameter 0.75 mm (30 mil) coefficient of thermal expansion 12.3 ppm/ c millimeters dim mim max a 1.52 1.80 a1 0.70 0. 9 0 a2 ? 0.6 b 0.82 0. 9 3 d 25 bsc d1 ? 11.3 d2 8 ? d3 ? 6.5 d4 7.2 7.4 e 1.27 bsc e 25 bsc e1 ? 11.3 e2 8 ? e3 ? 6.5 e4 7. 9 8.1 c a 360x b 0.3 a 0.15 b 0.2 2x a1 corner capacitor region 0.35 a d e e 0.2 2x c b a b c d e f g h j k l m n p r t u w v 1 d3 e2 e1 e4 d4 e3 d1 d2 1 2 345 6 78 9 10 11 12 13 14 15 16 17 18 1 9 0.15 a a a a1 a2 notes: 1. dimensioning and tolerance per asme y14.5m, 1 99 4. 2. dimensions in millimeters. 3. top side a1 corner index is a metalized feature with various shapes. bottom side a1 corner is designated with a pad missing from the array.
31 0814g?hirel?04/09 e2v semiconductors sas 2009 pc7448 8.6 mechanical dimensions for the pc7448, 360 hitce rohs-compliant bga figure 8-1 on page 29 provides the mechanical dimensions and bottom surface nomenclature for the pc7448, 360 hitce bga package with rohs-compliant lead-free spheres. figure 8-3. mechanical dimensions and bottom surface nomencla ture for the pc7448, 3 60 hitce rohs-compliant bga package a 0.15 a 0.35 a a a1 a2 a3 millimeters dim min max a 1. 9 2 2.40 a1 0.40 0.60 a2 0.70 0. 9 0 a3 ? 0.6 b 0.60 0. 9 0 d 25 bsc d1 ? 11.3 d2 8 ? d3 ? 6.5 d4 7.2 7.4 e 1.27 bsc e 25 bsc e1 ? 11.3 e2 8 ? e3 ? 6.5 e4 7. 9 8.1 4 c a 360x b 0.3 a 0.15 b 0.2 2x a1 corner capacitor region d e e 0.2 2x c b a b c d e f g h j k l m n p r t u w v 1 d3 e2 e1 e4 d4 e3 d1 d2 1 2 345 6 78 9 10 11 12 13 14 15 16 17 18 1 9 notes: 1. dimensioning and tolerance per asme y14.5m, 1 99 4. 2. dimensions in millimeters. 3. top side a1 corner index is a metallized feature with various shapes. bottom side a1 corner is designated with a ball missing from the array. 4. dimension a1 represents the collapsed sphere diameter.
32 0814g?hirel?04/09 pc7448 e2v semiconductors sas 2009 9. system design information this section provides system and thermal desig n requirements and recommendations for successful application of the pc7448. 9.1 clocks the following sections provide more detailed information regarding the clocking of the pc7448. 9.1.1 pll configuration the pc7448 pll is configured by the pll_cfg[0:5] signals. for a given sysclk (bus) frequency, the pll configuration signals set the internal cpu and vco frequency of operation. the pll configuration for the pc7448 is shown in table 9-1 . in this example, shaded cells represent settings that, for a given sysclk frequency, result in core and/or vco frequencies that do not comply with table 5-8 on page 16 . when enabled, dynamic frequency switching (dfs) also affects the core frequency by halving or quartering the bus-to-core multiplier; see section 9.7.5 ?dynamic frequency switching (dfs)? on page 49 , for more information. note that when dfs is enabled the resulting core frequency must meet the adjusted minimum core frequency requirements (f core_dfs ) described in table 5-8 on page 16 . note that the pll_cfg[5] is currently used for factory test only and should be tied low, and that the pc7448 pll configuration settings are compatible with the pc7447a pll configuration settings when pll_cfg[5] = 0.
33 0814g?hirel?04/09 e2v semiconductors sas 2009 pc7448 notes: 1. pll_cfg[0:5] settings not listed are reserved. table 9-1. pc7448 microprocessor pll configuration example pll_cfg[0:5] example core and vco frequency in mhz bus-to-core multiplier (5) core-to-vco multiplier (5) bus (sysclk) frequency 33.3 mhz 50 mhz 66.6 mhz 75 mhz 83 mhz 100 mhz 133 mhz 167 mhz 200 mhz 010000 2x 1x 100000 3x 1x 600 101000 4x 1x 667 800 101100 5x 1x 667 835 1000 100100 5.5x 1x 733 919 1100 110100 6x 1x 600 800 1002 1200 010100 6.5x 1x 650 866 1086 1300 001000 7x 1x 700 931 1169 1400 000100 7.5x 1x 623 750 1000 1253 1500 110000 8x 1x 600 664 800 1064 1336 1600 011000 8.5x 1x 638 706 850 1131 1417 1700 011110 9x 1x 600 675 747 900 1197 1500 011100 9.5x 1x 633 712 789 950 1264 1583 101010 10x 1x 667 750 830 1000 1333 1667 100010 10.5x 1x 700 938 872 1050 1397 100110 11x 1x 733 825 913 1100 1467 000000 11.5x 1x 766 863 955 1150 1533 101110 12x 1x 600 800 900 996 1200 1600 111110 12.5x 1x 625 833 938 1038 1250 1667 010110 13x 1x 650 865 975 1079 1300 111000 13.5x 1x 675 900 1013 1121 1350 110010 14x 1x 700 933 1050 1162 1400 000110 15x 1x 750 1000 1125 1245 1500 110110 16x 1x 800 1066 1200 1328 1600 000010 17x 1x 850 1132 1275 1417 1700 001010 18x 1x 600 900 1200 1350 1500 001110 20x 1x 667 1000 1332 1500 1666 010010 21x 1x 700 1050 1399 1575 011010 24x 1x 800 1200 1600 111010 28x 1x 933 1400 001100 pll bypass pll off, sysclk cl ocks core circuitry directly 111100 pll off pll off, no core clocking occurs
34 0814g?hirel?04/09 pc7448 e2v semiconductors sas 2009 2. the sample bus-to-core frequencies show n are for reference only. some pll configurations may select bus, core, or vco frequencies which are not useful, not suppor ted, or not tested for by the pc7448; see section 5.5.1 ?clock ac specifica- tions? on page 16 , for valid sysclk, core, and vco frequencies. 3. in pll-bypass mode, the sysclk input signal clocks the internal processor directly and the pll is disabled. however, the bus interface unit requires a 2x clock to function. therefore, an additional signal, ext_qual, must be driven at half the fre- quency of sysclk and offset in phase to meet the required input setup t ivkh and hold time t ixkh (see table 5-9 on page 18 ). the result will be that the processor bus frequency will be one-half sysclk, while the internal processor is clocked at sysclk frequency. this mode is intended for factory use and emulator tool use only. note : the ac timing specifications given in this document do not apply in pll-bypass mode. 4. in pll-off mode, no clocking occurs insi de the pc7448 re gardless of the sysclk input. 5. applicable when dfs modes are disabled. these multipliers change when operating in a dfs mode. 9.1.2 system bus clock (sysclk) and spread spectrum sources spread spectrum clock sources are an increasingly popular way to control electromagnetic interference emissions (emi) by spreading the emitted noise to a wider spectrum and reducing the peak noise magni- tude in order to meet industry and government requirements. these clock sources intentionally add long- term jitter in order to diffuse the emi spectral content. the jitter specification given in table 5-8 on page 16 considers short-term (cycle-to-cycle) jitter only and the clock generator?s cycle-to-cycle output jit- ter should meet the pc7448 input cy cle-to-cycle jitter requirement. frequency modulation and spread are separate concerns, and the pc7448 is compatible with spread spectrum sources if the recommendations listed in table 9-2 are observed. notes: 1. guaranteed by design. 2. sysclk frequencies resulting from frequency spreading, and the resulting core and vco frequencies, must meet the minimum and maxi mum specifications given in table 5-8 on page 16 . it is imperative to note that the processor?s minimum and maximum sysclk, core, and vco frequen- cies must not be exceeded regardless of the type of clock source. therefore, systems in which the processor is operated at its maximum rated core or bus frequency should avoid violating the stated limits by using down-spreading only. table 9-2. spread spectrum clock source recommendations parameter min max unit notes frequency modulation ? 50 khz (1) frequency spread ? 1 % (1)(2)
35 0814g?hirel?04/09 e2v semiconductors sas 2009 pc7448 9.2 power supply d esign and sequencing the following sections provide detailed information regarding power supply design for the pc7448. 9.2.1 power supply sequencing the pc7448 requires its power rails and clock to be applied in a specific sequence to ensure proper device operation and to prevent device damage. th e power sequencing requirements are as follows: ?av dd must be delayed with respect to v dd by the rc time constant of the pll filter circuit described in section 9.2.2 ?pll power supply filtering? on page 36 . this time constant is nominally 100 s. ?ov dd may ramp anytime before or after v dd and av dd . additionally, the following re quirements exist regarding the application of sysclk: ? the voltage at the sysclk input must not exceed v dd until v dd has ramped to 0.9 v. ? the voltage at the sysclk input must not exceed ov dd by more 20% during transients (see overshoot/undershoot specifications in figure 5-1 on page 11 ) or 0.3v dc (see table 5-3 on page 12 ) at any time. these requirements are shown graphically in figure 9-1 . figure 9-1. pc7448 power up sequencing requirements certain stipulations also apply to the manner in which the power rails of the pc7448 power down, as follows: ?ov dd may ramp down any time before v dd . no restrictions apply in this case. ?if ov dd ramps down with or after v dd , then ov dd must not exceed v dd by more than 1.4v during power down (v dd below 90% of its nominal value, see table 5-3 on page 12 ), as shown in figure 9-2 . av dd v dd ov dd sysclk 0.9 v no restrictions between ov dd and v dd 0.9 v limit imposed by v dd if ov dd ramps up first limit imposed by ov dd if v dd ramps up first 100 s (nominal) delay from v dd to av dd
36 0814g?hirel?04/09 pc7448 e2v semiconductors sas 2009 figure 9-2. pc7448 power down sequencing requirements there is no requirement regarding av dd during power down, but it is recommended that av dd track v dd within the rc time constant of the pll filter circuit described in section 9.2.2 ?pll power supply filter- ing? on page 36 (nominally 100 s). 9.2.2 pll power supply filtering the av dd power signal is provided on the pc7448 to pr ovide power to the clock generation pll. to ensure stability of the internal cl ock, the power supplied to the av dd input signal should be filtered of any noise in the 500-khz to 10-mhz resonant frequency range of the pll. the circuit shown in figure 9-3 using surface mount capacitors with minimum effect ive series inductance ( esl) is strongly recom- mended. in addition to filtering noise from the av dd input, it also provides the required delay between v dd and av dd as described in section 9.2.1 ?power supply sequencing? on page 35 . the circuit should be placed as close as possible to the av dd pin to minimize noise coupled from nearby circuits. it is often possible to route directly from the capacitors to the av dd pin, which is on the periphery of the device footprint. figure 9-3. pll power supply filter circuit v dd ov dd no restrictions between v dd and ov dd sysclk 0.9v av dd no restrictions between v dd and av dd note also restrictions between sysclk and ov dd 0.9v limit imposed by v dd if v dd ramps down first limit imposed by ov dd if ov dd ramps down first v dd 10 2.2 f 2.2 f gnd av dd low esl surface mount capacitors
37 0814g?hirel?04/09 e2v semiconductors sas 2009 pc7448 9.2.3 transient specifications the ensure the long-term re liability of the device, the pc7448 require s that transients on the core power rail (v dd ) be constrained. the recommended operating voltage specifications provided in table 5-3 on page 12 are dc specifications. that is, the dev ice may be operated continuously with v dd within the specified range without adversely affecting the device?s reliability. excursions above the stated recom- mended operation ra nge, including oversh oot during power-up, can impact the long-term re liability of the device. excursions are described by their amplitude an d duration. duration is defined as the time period during which the v dd power plane, as measured at the vdd_se nse pins, will be withi n a specific volt- age range, expressed as percentage of the total time the device will be powered up over the device lifetime. in practice, the period over which transients are measured can be any arbitrary period of time that accurately represents the expected range of processor and system activity. the voltage ranges and durations for normal operation and transients are described in table 9-3 . notes: 1. permitted duration is defined as the percentage of the total time the device is powered on that the v dd power supply voltage may exist within the specified voltage range. 2. see table 5-3 on page 12 for nominal v dd specifications. 3. to simplify measurement, excursions into the high transient region are included in this duration. 4. excursions above the absolute maximum rating of 1.4v are not permitted; see table 5-1 on page 11 . note that, to simplify transient measurements, the duration of the excursion into the high transient region is also included in the low transient duration, so that only the time the voltage is above each threshold must be considered. figure 9-4 on page 37 shows an example of measuring voltage transients. figure 9-4. voltage transient example table 9-3. v dd power supply transient specificatins (at recommended operating conditions, see table 5-3 on page 12 ) voltage region voltage range (v) permitted duration notes min max normal v dd minimum v dd maximum 100% low transient v dd maximum 1.35v 10% high transient 1.35v 1.40v 0.2% v dd (nominal) 1.40v a + b < t 10% 1.35v v dd (maximum) v dd (minimum) a c b t c < t 0.2% normal low transient high transient
38 0814g?hirel?04/09 pc7448 e2v semiconductors sas 2009 9.2.4 decoupling recommendations due to the pc7448 dynamic power management feature, large address and data buses, and high oper- ating frequencies, the pc7448 can generate transient power surges and high frequency noise in its power supply, especially wh ile driving large capacitive loads. th is noise must be prevented from reach- ing other components in the pc7448 system, and the pc7448 itself requires a clean, tightly regulated source of power. therefore, it is recommended t hat the system designer use sufficient decoupling capacitors, typically one capacitor for every 1?2 v dd pins, and a similar or lesser amount for the ov dd pins, placed as close as possible to the power pins of the pc 7448. it is also recommended that these decoupling capacitors receive their power from separate v dd , ov dd , and gnd power planes in the pcb, utilizing short traces to minimize inductance. these capacitors should have a value of 0.01 or 0.1 f. only ceramic surface mount technology (smt) capacitors should be used to minimize lead indu ctance. orientations where connections are made along the length of the part, such as 0204, are preferable but not mandatory. consistent with the recommenda- tions of dr. howard johnson in hig h speed digital design: a handboo k of black magic (prentice hall, 1993) and contrary to previous recommendations for decoupling freescale microprocessors, multiple small capacitors of equal value are recommended over using multiple values of capacitance. in addition, it is recommended that there be several bulk storage capacitors distributed around the pcb, feeding the v dd and ov dd planes, to enable quick recharging of the smaller chip capacitors. these bulk capacitors should have a low equivalent series resistance (esr) rating to ensure the quick response time necessary. they should also be connected to the power and ground planes through two vias to min- imize inductance. suggested bulk capacitors are 100?330 f (avx tps tantalum or sanyo oscon). 9.3 connection recommendations to ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. unless otherwise noted, unused ac tive low inputs should be tied to ov dd and unused active high inputs should be connected to gnd. all nc (no connect) signals must remain unconnected. power and ground connections must be made to all external v dd , ov dd , and gnd pins in the pc7448. for backward compatibility with the pc 7447, or for migrating a system or iginally designed for this device to the pc7448, the new power and ground signals (formerly nc, see table 7-1 on page 25 ) may be left unconnected if the core frequency is 1 ghz or less. operation above 1 ghz requires that these addi- tional power and ground signals be connected, and it is strongly recommended that all new designs include the additional connections. see also section 7. ?pinout listings? on page 25 , for additional information.
39 0814g?hirel?04/09 e2v semiconductors sas 2009 pc7448 9.4 output buffer dc impedance the pc7448 processor bus drivers are characterized over process, voltage, and temperature. to mea- sure z0, an external resistor is connected from the chip pad to ov dd or gnd. the value of each resistor is varied until the pad voltage is ov dd /2. figure 9-5 shows the driver impedance measurement. figure 9-5. driver impedance measurement the output impedance is the average of two components, the resistances of the pull-up and pull-down devices. when data is held low, sw2 is closed (sw1 is open), and rn is trimmed until the voltage at the pad equals ov dd /2. rn then becomes the resistance of the pull-down devices. when data is held high, sw1 is closed (sw2 is open), and rp is tr immed until the voltage at the pad equals ov dd /2. rp then becomes the resistance of the pull-up devices. rp and rn are designed to be close to each other in value. then, z0 = (rp + rn)/2. table 9-4 summarizes the signal impedance results. t he impedance increases with junction tempera- ture and is relatively unaffected by bus voltage. 9.5 pull-up/pull-down resistor requirements the pc7448 requires high-resistive (weak: 4.7-k ) pull-up resistors on several control pins of the bus interface to maintain the control signals in the negated state after they have been actively negated and released by the pc7448 or other bus masters. these pins are: ts , artry , shdo , and shd1 . some pins designated as being factory test pins must be pulled up to ov dd or down to gnd to ensure proper device operation. the pins that must be pulled up to ov dd are lssd_mode and test[0:3]; the pins that must be pulled down to gnd are l1_tstclk and test[4]. the ckstp_in signal should like- wise be pulled up through a pull-up resistor (weak or stronger: 4.7?1 k ) to prevent erroneous assertions of this signal. table 9-4. impedance characteristics (at recommended operating conditions, see table 5-3 on page 12 ) impedance processor bus l3 bus unit z 0 typical 33 ? 42 34 ? 42 maximum 31 ? 51 32 ? 44 ov dd ognd sw2 sw1 rn rp pad data
40 0814g?hirel?04/09 pc7448 e2v semiconductors sas 2009 in addition, the pc7448 has one open-drain style output that requires a pull-up resistor (weak or stron- ger: 4.7?1 k ) if it is used by the system. this pin is ckstp_out . bvsel0 and bvsel1 should not be allowed to float, and should be config ured either via pull-up or pull- down resistors or actively driven by external logic. if pul l-down resistors are us ed to configure bvsel0 or bvsel1, the resistors should be less than 250 (see table 7-1 on page 25 ). because pll_cfg[0:5] must remain stable during normal operation, strong pull-up and pull-down resistors (1 k or less) are recommended to configure these signals in order to protect against erroneous switching due to ground bounce, power supply noise, or noise coupling. during inactive periods on the bus, the address and transfer attributes may not be driven by any master and may, therefore, float in the high-impedance stat e for relatively long peri ods of time. because the pc7448 must continually monitor these signals for snooping, this float condition may cause excessive power draw by the input receivers on the pc7448 or by other receivers in the system. these signals can be pulled up through weak (10 k ) pull-up resistors by the system, address bus driven mode enabled (see the pc7450 risc microprocessor family users? manual for more information on this mode), or they may be otherwise driven by the system during i nactive periods of the bus to avoid this additional power draw. preliminary studies have shown the additional power draw by the pc7448 input receivers to be negligible and, in any event, none of these measures are necessary for proper device operation. the snooped address and transfer attribute inputs are: a[0:35], ap[0:4], tt[0:4], ci , wt , and gbl . if address or data parity is not used by the system , and respective parity checking is disabled through hid1, the input receivers for those pins are disabled and do not require pull-up resistors, therefore they may be left uncon nected by the system. if ex tended addressing is not used (hid0[xaen ] = 0), a[0:3] are unused and must be pulled low to gnd through weak pull-down resistors; additionally, if address parity checking is enabled (hid1[eba] = 1) and extended addressing is not used, ap[0] must be pulled up to ov dd through a weak pull-up resistor. if the pc7448 is in 60x bus mode, dti[0:3] must be pulled low to gnd through weak pull-down resistors. the data bus input receivers are normally turned off when no read operation is in progress and, there- fore, do not require pull-up resistors on the bus. other data bus receivers in the system, however, may require pull-ups or require that those signals be ot herwise driven by the system during inactive periods. the data bus signals are d[0:63] and dp[0:7]. 9.6 jtag configuration signals boundary-scan testing is enabled through the jtag interface signals. the trst signal is optional in the ieee 1149.1 specification, but is provided on all pr ocessors that implement the powerpc architecture. while it is possible to force the tap controller to the reset state using only the tck and tms signals, more reliable power-on reset performance will be obtained if the trst signal is asserted during power- on reset. because the jtag interface is also used for accessing the common on-chip processor (cop) function, simply tying trst to hreset is not practical. the cop function of these processors allows a remote computer system (typically a pc with dedicated hardware and debugging software) to access and control the internal operations of the processor. the cop interface connects primarily through the jtag port of the processor, with some additional status monitoring signals. the cop port requires the ability to independently assert hreset or trst in order to fully control the processor. if the target system has independent reset sources, such as voltage moni- tors, watchdog timers, power supply failures, or push-button switches, then the cop reset signals must be merged into these signals with logic.
41 0814g?hirel?04/09 e2v semiconductors sas 2009 pc7448 the arrangement shown in figure 9-6 on page 42 allows the cop port to independently assert hreset or trst , while ensuring that th e target can drive hreset as well. if the jtag interface and cop header will not be used, trst should be tied to hreset through a 0 . isolation resistor so that it is asserted when the system reset signal (hreset ) is asserted, ensuring that the jtag scan chain is ini- tialized during power-on. although freescale recommends that the cop header be designed into the system as shown in figure 9-6 , if this is not possible, the isolat ion resistor will allo w future access to trst in the case where a jtag interface may need to be wired onto the system in debug situations. the cop header shown in figure 9-6 adds many benefits: breakpoints, watchpoints, register and mem- ory examination/modification, and other standard debugger features are possible through this interface and can be as inexpensive as an unpopulated footprint for a header to be added when needed. the cop interface has a standard header for connection to the target system, based on the 0.025" square-post, 0.100" centered header assembly (often called a berg header). the connector typically has pin 14 removed as a connector key. there is no standardized way to number the cop header shown in figure 9-6 ; consequently, many dif- ferent pin numbers have been observed from emulator vendors. some are numbered top-to-bottom then left-to-right, while others use left-to-right then top- to-bottom, while still others number the pins counter clockwise from pin 1 (as with an ic). regardless of the numbering, the signal placement recommended in figure 9-6 is common to all known emulators. the qack signal shown in figure 9-6 is usually connected to the pci bridge chip in a system and is an input to the pc7448 informing it that it can go into the quiescent state. under normal operation this occurs during a low-power mode selection. in order for cop to work, the pc7448 must see this signal asserted (pulled down). while shown on the cop header, not all emulator products drive this signal. if the product does not, a pull-down resistor can be populated to assert this signal. additionally, some emulator products implement open-drain type outputs and can only drive qack asserted; for these tools, a pull-up resistor can be implemented to ensure this signal is negated when it is not being driven by the tool. note that the pull-up and pull-down resistors on the qack signal are mutu- ally exclusive and it is never necessary to popula te both in a system. to pr eserve correct power-down operation, qack should be merged through logic so that it also can be driven by the pci bridge.
42 0814g?hirel?04/09 pc7448 e2v semiconductors sas 2009 figure 9-6. jtag interface connection notes: 1. run/stop , normally found on pin 5 of the cop header, is not implemented on the pc7448. connect pin 5 of the cop header to ov dd with a 10 k pull-up resistor. 2. key location; pin 14 is not physically present on the cop header. 3. component not populated. populate only if debug tool does not drive qack . 4. populate only if debug tool uses an open-drai n type output and does not actively negate qack . 5. if the jtag interface is implemented, connect hreset from the target source to trst from the cop header though an and gate to trst of the part. if the jtag inte rface is not implemented, connect hreset from the target source to trst of the part through a 0 isolation resistor. 6. the cop port and target board should be able to independently assert hreset and trst to the pro- cessor in order to fully control the processor as shown above. hreset hreset (6) hreset 13 sreset sreset sreset 11 vdd_sense 6 5 (1) 15 2 k 10 k 10 k 10 k ov dd ov dd ov dd ov dd chkstp_in chkstp_in 8 tms tdo tdi tck tms tdo tdi tck 9 1 3 4 trst 7 16 2 10 14 (2) key qack ov dd ov dd ov dd trst (6) 10 k 10 k 10 k 10 k ov dd qack qack chkstp_out chkstp_out 3 13 9 5 1 6 10 2 15 11 7 16 12 8 4 key no pin cop connector physical pin out 10 k (4) ov dd ov dd 1 2 k (3) 0 (5) 12 nc nc from target board sources (if any) cop header 10 k
43 0814g?hirel?04/09 e2v semiconductors sas 2009 pc7448 9.7 thermal management information this section provides thermal management information for the high coefficient of thermal expansion (hitce) package for air-cooled applications. proper thermal control design is pr imarily dependent on the system-level design, the heat sink, airflow, and t hermal interface material. the pc7448 implements sev- eral features designed to assist with thermal management, including dfs and the temperature diode. dfs reduces the power consumption of the device by reducing the core frequency; see section 9.7.5.1 ?power consumption with dfs enabled? on page 50 , for specific information regarding power reduction and dfs. the temperature diode allows an external device to monitor the die temperature in order to detect excessive temperature conditions and alert the system; see section 9.7.4 ?temperature diode? on page 48 , for more information. to reduce the die-junction temperature, heat sinks may be attached to the package by several methods, spring clip to holes in the printed-circuit board or package, and mounting clip and screw assembly (see figure 9-7 ); however, due to the potential large mass of the heat sink, attachment through the printed- circuit board is suggested. in any implementation of a heat sink solution, the force on the die should not exceed ten pounds. figure 9-7. bga package exploded cross-sectional view with several heat sink options note: a clip on heat sink is not recommended for lg a because there may not be adequate clearance between the device and the circuit board.. a through-hole solution is recommended, as shown in figure 9-8 below. printed-circuit board thermal interface material heat sink clip heat sink hcte bga package
44 0814g?hirel?04/09 pc7448 e2v semiconductors sas 2009 figure 9-8. lga package exploded cross-sectional view with several heat sink options 9.7.1 internal package conduction resistance for the exposed-die packaging technology described in table 5-4 on page 13 , the intrinsic conduction thermal resistance paths are as follows: ? the die junction-to-case thermal resistance (the case is actua lly the top of the exposed silicon die) ? the die junction-to-ball thermal resistance figure 9-5 on page 39 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board. figure 9-9. c4 package with heat sink mounted to a printed-circuit board note the internal versus external package resistance. heat generated on the active side of the chip is conducted through the silicon, through the heat sink attach material (or thermal interface material), and, finally, to the heat sink, where it is removed by forced-air convection. because the silicon thermal resistance is quite smal l, the temperature drop in the silicon may be neglected for a first-order analysis. thus, the ther mal interface material and the heat sink conduc- tion/convective thermal resistances are the dominant terms. printed-circuit board thermal interface material heat sink clip heat sink hcte lga package external resistance external resistance internal resistance radiation convection heat sink thermal interface material die/package die junction package/leads printed-circuit board radiation convection
45 0814g?hirel?04/09 e2v semiconductors sas 2009 pc7448 9.7.2 thermal inte rface materials a thermal interface material is recommended at the package lid-to-heat sink interface to minimize the thermal contact resistance. for those applications w here the heat sink is attached by spring clip mecha- nism, figure 9-10 shows the thermal performance of three thin-sheet thermal-interface materials (silicone, graphite/oil, fluor oether oil), a bare joint, and a joint with th ermal grease as a function of contact pressure. as shown, the performance of these thermal interface materials improves with increasing con- tact pressure. the use of thermal grease significantly reduces the interface thermal resistance. that is, the bare joint results in a thermal resistance approximately seven times greater than the thermal grease joint. often, heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see figure 9-7 on page 43 ). therefore, synthetic grease offers the best thermal performance due to the low interface pressure and is recommended due to the high power dissipation of the pc7448. of course, the selection of any thermal interface material depends on many factors, thermal performance requirements, manufactur ability, service temperature, dielec tric properties, cost, and so on. figure 9-10. thermal performance of select thermal interface material the board designer can choose between several types of thermal interfaces. heat sink adhesive materi- als should be selected based on high conductivity and mechanical strength to meet equipment shock/vibration requirements. 0 0.5 1 1.5 2 010 20304050607080 silicone sheet (0.006 in.) bare joint floroether oil sheet (0.007 in.) graphite/oil sheet (0.005 in.) synthetic grease contact pressure (psi) specific thermal resistance (k-in. 2 /w)
46 0814g?hirel?04/09 pc7448 e2v semiconductors sas 2009 there are several commercially available thermal inte rfaces and adhesive materials provided by the fol- lowing vendors: the bergquist company 800-347-4572 18930 west 78th st. chanhassen, mn 55317 internet: www.bergquistcompany.com chomerics, inc. 781-935-4850 77 dragon ct. woburn, ma 01801 internet: www.chomerics.com dow-corning corporation 800-248-2481 corporate center p.o. box 994. midland, mi 48686-0994 internet: www.dowcorning.com shin-etsu microsi, inc. 888-642-7674 10028 s. 51st st. phoenix, az 85044 internet: www.microsi.com thermagon inc. 888-246-9050 4707 detroit ave. cleveland, oh 44102 internet: www.thermagon.com the following section provides a heat sink selecti on example using one of the commercially available heat sinks. 9.7.3 heat sink selection example for preliminary heat sink sizing, the die-junc tion temperature can be expressed as follows: t j = t i + t r + (r jc + r int + r sa ) p d where: t j is the die-junction temperature t i is the inlet cabinet ambient temperature t r is the air temperature rise within the computer cabinet r jc is the junction-to-case thermal resistance r int is the adhesive or interface material thermal resistance r sa is the heat sink base-to-ambient thermal resistance p d is the power dissipated by the device
47 0814g?hirel?04/09 e2v semiconductors sas 2009 pc7448 during operation, the die-junction temperatures (t j ) should be maintained less than the value specified in table 5-3 on page 12 . the temperature of air cooling the component greatly depends on the ambient inlet air temperature and the air temperature rise withi n the electronic cabinet. an electronic cabinet inlet- air temperature (t i ) may range from 30 to 40 c. the air temperature rise within a cabinet (t r ) may be in the range of 5 to 10 c. the thermal resistance of the thermal interface material (r int ) is typically about 1.1 c/w. for example, assuming a t i of 30 c, a t r of 5 c, an hitce package r jc = 0.1, and a typical power consumption (p d ) of 21w, the following expression for t j is obtained: die-junction temperature: t j = 30 c + 5 c + (0.1 c/w + 1.1 c/w + sa ) 25.6 for this example, a r sa value of 1.53 c/w or less is required to maintain the die junction temperature below the maximum value of table 5-3 on page 12 . though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common fig- ure-of-merit used for comparing the thermal per formance of various microelectronic packaging technologies, one should exercise caution when only using this metric in determining thermal manage- ment because no single parameter can adequately descr ibe three-dimensional heat flow. the final die- junction operating temperature is not only a function of the component-level thermal resistance, but the system-level design and its operating conditions. in addition to the component's power consumption, a number of factors affect the final operating die-junction temperature: airflow, board population (local heat flux of adjacent components), heat sink efficiency, heat sink attach, heat sink placement, next-level inter- connect technology, system air temperature rise, altitude, and so on. due to the complexity and variety of system-level bo undary conditions for toda y's microelectronic equip- ment, the combined effects of the heat transfer mechanisms (radiation, convection, and conduction) may vary widely. for these reasons, we recommend using conjugate heat transfer models for the board as well as system-level designs. for system thermal modeling, the pc7448 thermal model is shown in figure 9-11 on page 48 . four vol- umes represent this device. two of the volumes, solder ball-air and substrate, are modeled using the package outline size of the package .the other two, die an d bump-underfill, have the same size as the die. the silicon die should be modeled 8.0 7.3 0.86 mm 3 with the heat source applied as a uniform source at the bottom of the volume. the bump and underfill layer is model ed as 8.0 7.3 0.07 mm 3 collapsed in the z-direction with a thermal conductivity of 5.0 w/(m ? k) in the z-direction. the substrate volume is 25 25 1.14 mm 3 and has 9.9 w/(m ? k) isotropic conductivity in the xy-plane and 2.95 w/(m ? k) in the direction of the z-axis. the solder ball and air layer are modeled with the same horizontal dimensions as the substrate and is 0.8 mm thick. fo r the lga package the solder and air layer is 0.1 mm thick, but the material properties are the same. it can also be modeled as a collapsed volume using orthotropic material properties: 0.034 w/(m ? k) in the xy-plane direction and 11.2 w/(m ? k) in the direc- tion of the z-axis.
48 0814g?hirel?04/09 pc7448 e2v semiconductors sas 2009 figure 9-11. recommended thermal model of pc7448 9.7.4 temperature diode the pc7448 has a temperature diode on the microprocessor that can be used in conjunction with other system temperature monitoring devices (such as analog devices, adt7461 ? ). these devices use the negative temperature coefficient of a diode operated at a constant current to determine the temperature of the microprocessor and its environment. for proper operation, the monitoring device used should auto-calibrate the device by canceling out the v be variation of each pc7448?s internal diode. the following are the specifications of the pc7448 on-board temperature diode: v f > 0.40v v f < 0.90v operating range 2 - 300 a diode leakage < 10 na at 125 c ideality factor over 5 a ? 150 a at 60 c: n = 1.0275 0.9% ideality factor is defined as the deviation from the ideal diode equation: another useful equation is: bump and underfill die substrate solder and air die top view of model (not to scale) side view of model (not to scale) x y z conductivity value unit die (8.0 x 7.3 x 0.86 mm ) silicon temperature- dependent w/(m ? k) w/(m ? k) w/(m ? k) w/(m ? k) bump and underfill (8.0 x 7.3 x 0.07 mm ) k z 5.0 substrate (25 x 25 x 1.14 mm ) k x 9.9 k y 9.9 k z 2.95 k x 0.034 k y 0.034 k z 11.2 substrate 3 3 3 solder ball and air (25 x 25 x 0.8 mm ) 3 i fw i s e qv f nkt ---------- - 1 ? = v h v l ? n kt q ------- ln i h i l ----- 1 ? =
49 0814g?hirel?04/09 e2v semiconductors sas 2009 pc7448 where: i fw = forward current i s = saturation current v d = voltage at diode v f = voltage forward biased v h = diode voltage while i h is flowing v l = diode voltage while i l is flowing i h = larger diode bias current i l = smaller diode bias current q = charge of electron (1.6 10 -19 c) n = ideality factor (normally 1.0) k = boltzman?s constant (1.38 10 -23 joules/k) t = temperature (kelvins) the ratio of i h to i l is usually selected to be 10:1. the above simplifies to the following: v h - v l = 1.986 10 -4 nt solving for t, the equation becomes: 9.7.5 dynamic frequency switching (dfs) the dfs feature in the pc7448 adds the ability to divide the processor-to -system bus ratio by two or four during normal functional operation. divide-by-two mode is enabled by setting the hid1[dfs2] bit in soft- ware or by asserting the dfs2 pin via hardware. the pc7448 can be returned for full speed by clearing hid1[dfs2] or negating dfs2 . similarly, divide-by-four mode is en abled by setting hid1[dfs4] in soft- ware or by asserting the dfs4 pin. in all cases, the frequency ch ange occurs in 1 clock cycle and no idle waiting period is required to switch between modes. note that asserting either dfs2 or dfs4 overrides software control of dfs, and that asserting both dfs2 and dfs4 disables dfs completely, including software control. additional information regardi ng dfs can be found in the pc7450 risc microproces- sor family reference manual. note that minimum core frequency requirements must be observed when enabling dfs, and the resulting core frequency must meet the requirements for f core_dfs given in table 5-8 on page 16 . nt v h v ? l 1.986 10 4 ? ----------------------------------- - =
50 0814g?hirel?04/09 pc7448 e2v semiconductors sas 2009 9.7.5.1 power consumption with dfs enabled power consumption with dfs enabled can be approximated using the following formula: where: p dfs = power consumption with dfs enabled f dfs = core frequency with dfs enabled f = core frequency prior to enabling dfs p = power consumption prior to enabling dfs (see table 5-6 on page 15 ) p ds = deep sleep mode power consumption (see table 5-6 on page 15 ) the above is an approximation only. power consumption with dfs enabled is not tested or guaranteed. p dfs f dfs f ---------- - pp ds ? () p ds + =
51 0814g?hirel?04/09 e2v semiconductors sas 2009 pc7448 9.7.5.2 bus-to-core multip lier constraints with dfs dfs is not available for all bus-to-core multipliers as configured by pll_cfg[0:5] during hard reset. the complete listing is shown in table 9-5 . table 9-5. valid divide ratio configurations bus-to-core multiplier configured by pll_cfg[0:5] (see table 9-1 on page 33 ) bus-to-core multiplier with hid1[dfs2] = 1 or dfs2 = 0 (2) bus-to-core multiplier with hid1[dfs4] = 1 or dfs4 = 0 (4) 2x n/a n/a 3x n/a n/a 4x 2x n/a 5x 2.5x n/a 5.5x 2.75x n/a 6x 3x n/a 6.5x 3.25x n/a 7x 3.5x n/a 7.5x 3.75x n/a 8x 4x 2x 8.5x 4.25x n/a 9x 4.5x 2.25x 9.5x 4.75x n/a 10x 5x 2.5x 10.5x 5.25x n/a 11x 5.5x 2.75x 11.5x 5.75x n/a 12x 6x 3x 12.5x 6.25x n/a 13x 6.5x 3.25x 13.5x 6.75x n/a 14x 7x 3.5x 15x 7.5x 3.75x 16x 8x 4x 17x 8.5x 4.25x 18x 9x 4.5x 20x 10x 5x 21x 10.5x 5.25x 24x 12x 6x 28x 14x 7x
52 0814g?hirel?04/09 pc7448 e2v semiconductors sas 2009 9.7.5.3 minimum core frequency requirements with dfs in many systems, enabling dfs can result in very lo w processor core frequenc ies. however, care must be taken to ensure that the resulting processor co re frequency is within the limits specified in table 5-8 on page 16 . proper operation of the device is not guaranteed at core frequencies below the specified minimum f core . 10. ordering information notes: 1. for availability of the different versions, contact your local e2v sales office. 2. the letter x in the part number designates a "prototype" pr oduct that has not been qualified by e2v. reliability of a pcx par t- number is not guaranteed and such part-number shall not be us ed in flight hardware. product changes may still occur while shipping prototypes. 3. power consumption for the 600 mhz k-spec and 1267 mhz n- spec devices are intentionally constrained via testing and sorting to assure low power consumption for this device. 11. definitions 11.1 life support applications these products are not designed for use in life s upport appliances, devices or systems where malfunc- tion of these products can reasonably be expected to result in personal injury. e2v customers using or selling these products fo r use in such applications do so at thei r own risk and agree to fully indemnify e2v for any damages resulting from such improper use or sale. table 10-1. ordering information xx 7448 y xxx nnnn n x product code (1) part identifier temperature range (1) package (1) processor frequency application modifier revision level (1) pc(x) (2) 7448 v: t c = -40 c, t j = +110 c m: t c = -55 c, t j = +125 c f: t c = -40 c, t j = 125 c gh hi-tce cbga lh: hi-tce lga sh: rohs bga 600 mhz k: 1.0v 50 mv (3) d: 2.2 :pvr = 8004_0202 600 mhz n: 1.0v 50 mv 1000 mhz n: 1.0v 50 mv 1250 mhz n: 1.1v 50 mv 1267 mhz n: 1.05v 50 mv (3)
53 0814g?hirel?04/09 e2v semiconductors sas 2009 pc7448 12. document revision history table 12-1 provides a revision history for this hardware specification. table 12-1. document revision history revision number date substantive change(s) g 04/09 table 10-1 on page 52 : added new temperature range f 02/09 add 600 mhz parts modification - table 4-1 on page 10 - table 5-3 on page 12 - table 5-6 on page 15 - table 5-8 on page 16 - table 5-7 on page 16 - section 10. ?ordering information? on page 52 e 12/08 page 6: ?parity support on cache? replaced by ?parity support on l1 and l2 cache and l2 tags?. d 12/07 add 1267 mhz parts. c 08/07 "preliminary" status removed from this dat asheet consecutive to product qualification completion. b 02/07 name change from atmel to e2v. on first page: modifying typical/po wer consumption and maximum frequency. table 4-1 on page 10 : removed hitce in core power supply at 1000 mhz table 5-3 on page 12 : change operating temperature to t c = ? 55 ; t j = +125 table 5-6 on page 15 note 3 : change temperature to 125 c ordering information: - change processor frequency - associated v dd level - added rev d parts a 10/05 initial revision.
54 0814g?hirel?04/09 pc7448 e2v semiconductors sas 2009
i 0814g?hirel?04/09 e2v semiconductors sas 2009 pc7448 table of contents features............... ................. .............. .............. .............. .............. ............. 1 description ............... ................ ................. ................ ................. ............... 1 screening ............ ................. .............. .............. .............. .............. ............. 1 1 overview ........... ................ ................. .............. .............. .............. ............. 2 2 features .............. ................. .............. .............. .............. .............. ............. 4 3 comparison with the pc744 7a and pc7447 .............. .............. ............. 8 4 general parameters .. ................. ................ ................. ................ ........... 10 5 electrical and therma l characteristics ............... ............ ........... ......... 10 5.1 detailed specification ............................................................................................ 10 5.2 applicable documents ........................................................................................... 10 5.3 dc electrical characteristics ................................................................................. 11 5.4 voltage and frequency derating ........................................................................... 16 5.5 ac electrical characteristics ................................................................................. 16 6 pin assignments .......... ................ ................ ................. .............. ........... 24 7 pinout listings ........ ................ ................. ................ ................. ............. 25 8 package description .............. ................. ................ ................. ............. 28 8.1 package parameters for the pc7448, 360 hitce bga ....................................... 28 8.2 mechanical dimensions for the pc7448, 360 hitce bga ................................... 29 8.3 package parameters for the pc7448, 360 hitce lga ........................................ 29 8.4 mechanical dimensions for the pc7448, 360 hitce lga ................................... 30 8.5 package parameters for the pc7448, 360 hitce rohs-compliant bga ........... 30 8.6 mechanical dimensions for the pc7448, 360 hitce rohs-compliant bga .......31 9 system design information ... ................. ................ ................. ............. 32 9.1 clocks .................................................................................................................... 3 2 9.2 power supply design and sequencing .................................................................35 9.3 connection recommendations ............................................................................. 38 9.4 output buffer dc impedance ................................................................................ 39 9.5 pull-up/pull-down resistor requirements ............................................................. 39 9.6 jtag configuration signals .................................................................................. 40 9.7 thermal management information ........................................................................ 43
ii 0814g?hirel?04/09 pc7448 e2v semiconductors sas 2009 10 ordering information ............ .............. .............. .............. .............. ......... 52 11 definitions ............. .............. .............. .............. .............. .............. ........... 52 11.1 life support applications ..................................................................................... 52 12 document revision history .. ............. .............. .............. .............. ......... 53 table of contents ......... ................ ................ ................. ................ ............ i
0814g?hirel?04/09 e2v semiconductors sas 2009 whilst e2v has taken care to ensure the accuracy of the inform ation contained herein it accepts no responsibility for the conse quences of any use thereof and also reserves the right to change the specification of goods without notice. e2v accepts no liability beyond that set out i n its standard conditions of sale in respect of infringement of third party patents arising from the use of tubes or other devices in accordance with information contained herein. how to reach us home page: www.e2v.com sales offices: europe regional sales office e2v ltd 106 waterhouse lane chelmsford essex cm1 2qu england tel: +44 (0)1245 493493 fax: +44 (0)1245 492492 mailto: enquiries@e2v.com e2v sas 16 burospace f-91572 bivres cedex france tel: +33 (0) 16019 5500 fax: +33 (0) 16019 5529 mailto: enquiries-fr@e2v.com e2v gmbh industriestra?e 29 82194 gr?benzell germany tel: +49 (0) 8142 41057-0 fax: +49 (0) 8142 284547 mailto: enquiries-de@e2v.com americas e2v inc 520 white plains road suite 450 tarrytown, ny 10591 usa tel: +1 (914) 592 6050 or 1-800-342-5338, fax: +1 (914) 592-5148 mailto: enquiries-na@e2v.com asia pacific e2v ltd 11/f., onfem tower, 29 wyndham street, central, hong kong tel: +852 3679 364 8/9 fax: +852 3583 1084 mailto: enquiries-ap@e2v.com product contact: e2v avenue de rochepleine bp 123 - 38521 saint-egrve cedex france tel: +33 (0)4 76 58 30 00 hotline : mailto: std-hotline@e2v.com

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